1. Field of the Invention
The present invention relates to a buffer circuit and a buffer control method, and more particularly, to a buffer circuit capable of dynamically adjusting a buffer capacity based on a valid data amount to suitably reduce power consumption and a buffer control method of controlling the buffer circuit.
2. Description of the Related Art
Data transfer is generally performed between an input-output (I/O) device such as a hard disk and a memory through a buffer circuit. FIG. 13 shows a structural example of a conventional first-in first-out (FIFO) buffer circuit. As shown in FIG. 13, the FIFO buffer circuit includes a write control unit (WCU) 5, a read control unit (RCU) 6, and a data storage unit (DSU) 7.
A write enable signal (WE) 501 is a write enable signal from the outside. Write data (WD) 502 is write data from the outside. A read enable signal (RE) 601 is a read enable signal from the outside. Read data (RD) 602 is read data to the outside. A clock (clk) 100 is a synchronizing clock signal and used for timing control in each of the WCU 5, the RCU 6, and the DSU 7.
The WCU 5 includes a write pointer generator (WPG) 51 for generating a write pointer (wp) 56 based on the WE 501. The WCU 5 generates write data (wd) 57 based on the WD 502 and generates a write enable signal (we) 58 based on the WD 502. When the we 58 is 1, the WCU 5 writes the wd 57 into the DSU 7 at an address indicated by the wp 56.
The RCU 6 includes a read pointer generator (RPG) 61 for generating a read pointer (rp) 66 based on the RE 601. The RCU 6 reads read data (rd) 67 from the DSU 7 at an address indicated by the rp 66. When the RE 601 is 1, the RCU 6 generates the rd 67 as the RD 602.
The DSU 7 includes a buffer whose capacity is N words. The buffer has two buffer units, BU-A 71 and BU-B 72, each of whose capacity is N/2 words.
Hereinafter, the structures of the WCU 5, the RCU 6, and the DSU 7 will be described in detail with reference to the attached drawings.
The WCU 5 will be described in detail with reference to FIG. 14. The WCU 5 includes the WPG 51, a write data generator (WDG) 52, and a write enable generator (WEG) 53.
The WDG 52 synchronizes the WD 502 with the clk 100 and generates the wd 57. The WEG 53 synchronizes the WE 501 with the clk 100 and generates the we 58.
The WPG 51 includes a write pointer resister (WPR) 54 for holding the wp 56. A value held by the WPR 54 is added with 1 by an adder 55 at a timing of the next clock of the clock at which data is written. The WPR 54 generates addresses covering the entire area (N words) of the DSU 7. The WPG 51 can be realized using an N-bit ring counter (a scale-of-N counter).
In the DSU 7 located at a subsequent stage of the WCU 5, when the we 58 is 1, a value of the wd 57 is written into the DSU 7 at an address specified by the wp 56.
The RCU 6 will be described in detail with reference to FIG. 15. The RCU 6 includes the RPG 61, a read data generator (RDG) 62, and a read enable generator (REG) 63.
The REG 63 synchronizes the RE 601 with the clk 100 and generates a read enable signal (re) 68. The RDG 62 obtains the rd 67 from the DSU 7 in response to the re 68 and generates the RD 602.
The RPG 61 includes a read pointer register (RPR) 64 for holding the rp 66. A value held by the RPR 64 is added with 1 by an adder 65 at a timing of the next clock of the clock at which data is read. The RPR 64 generates addresses covering the entire area (N words) of the DSU 7. The RPG 61 can be realized using an N-bit ring counter.
The RCU 6 obtains the rd 67 from the DSU 7 an address specified by the rp 66, at a timing when the re 68 is 1. That is, the timing when the re 68 is 1 is an effective timing of the rd 67.
The DSU 7 will be described in detail with reference to FIG. 16. The buffer of the DSU 7 has the two buffer units (BU-A 71 and BU-B 72).
The DSU 7 generates a write enable signal (we-A) 73 to the BU-A 71 and a write enable signal (we-B) 74 to the BU-B 72 based on the we 58 and the wp 56. At this time, in order to select the BU-A 71 or the BU-B 72 as a destination of the wd 57, the wp 56 is divided into a write pointer (wp-MSB) 76 which is a most significant bit (MSB) and a write pointer (wp′) 75 including other bits. When the wp-MSB 76 is 0, the destination is the BU-A 71. When the wp-MSB 76 is 1, the destination is the BU-B 72.
That is, when the wp-MSB 76 is 0, the we-A 73 becomes 1. At this time, the wd 57 is written into the BU-A 71 at an address indicated by the wp′ 75 at a timing determined by the clk 100. When the wp-MSB 76 is 1, the we-B 74 becomes 1. At this time, the wd 57 is written into BU-B 72 at an address indicated by the wp′ 75 at a timing determined by the clk 100.
The DSU 7 generates read addresses for the BU-A 71 and the BU-B 72 based on the rp 66. At this time, in order to select read data (rd-A) 77 from the BU-A 71 or read data (rd-B) 78 from the BU-B 72, the rp 66 is divided into a read pointer (rp-MSB) 701 which is an MSB and a read pointer (rp′) 702 including other bits. When the rp-MSB 701 is 0, the rd-A 77 is selected by a selector 79. When the rp-MSB 701 is 1, the rd-B 78 is selected by the selector 79. The selected read data is outputted as the rd 67.
Hereinafter, the operation of the conventional FIFO buffer circuit having the above-mentioned structure will be described with reference to a timing diagram shown in FIG. 17. In order to facilitate understanding, a case where a buffer capacity N is set to 16 words, each of the wp 56 and the rp 66 has four bits to specify addresses 0 to 15 will be described as an example.
As shown in FIG. 17, when the WE 501 becomes 1 at a timing 0 (t0), the we 58 is changed to 1 at a timing 1 (t1). At this time, the wp 56 is 0, so the wp-MSB 76 is 0. Therefore, the we-A 73 becomes 1, so the wd 57 is written into BU-A 71 at an address 0. The wp 56 is added with 1 at a timing 2 (t2).
After that, the WE 501 is 0 for a period-between a timing 2 (t2) and a timing 8 (t8). Therefore, the we-A 73 is 1 for a period between a timing 3 (t3) and a timing 9 (t9), with the result that the wd 57 is written into BU-A 71 at each address specified by the wp′ 75 which is 0 to 7.
When the RE 601 becomes 1 at the timing 1 (t1), the re 68 is changed to 1 at the timing 2 (t2). At this time, the rp 66 is 0. Therefore, the rd-A 77 is read from the BU-A 71 at the address 0 and the rd-B 78 is read from the BU-B 72 at an address 0. The rp-MSB 701 is 0, so the rd-A 77 is outputted as the RD 602. The rp 66 is added with 1 at the timing 3 (t3).
After that, the RE 601 is 1 for periods related to timings, t3, t5, t6, and t8 to t15, so the re 68 is 1 for periods related to timings t4, t6, t7, and t9 to t16. Therefore, the rd-A 77 is selected from BU-A 71 at each address specified by the rp′ 702 which is 1 to 7 and outputted as the RD 602.
When the WE 501 becomes 1 at the timing 10 (t10), the we 58 is changed to 1 at the timing 11 (t11). At this time, the wp 56 is 8, so the wp-MSB 76 is 1. Therefore, the wd 57 is written into BU-B 72 at the address 0. Then, the rp 66 becomes 8 at the timing 13 (t13), so the rp-MSB) 701 is 1. Therefore, the rd-B 78 is selected from the address 0 of the BU-B 72 and outputted as the RD 602.
When the wp 56 returns to 0 at a timing 20 (t20), the wd 57 is written into BU-A 71 at the address 0. When the rp 66 returns to 0 at a timing 23 (t23), the rd-A 77 is selected from the address 0 of the BU-A 71 and outputted as the RD 602.
A technique related to a data transfer control apparatus using the above-mentioned FIFO buffer (FIFO memory) circuit is disclosed in Japanese Patent Application Laid-open No. 2003-36145.
The FIFO buffer circuit is constructed using a scale-of-N counter to be a ring buffer. Therefore, the conventional FIFO buffer circuit has the following problems to be pointed out.
The FIFO buffer circuit is controlled simply using the ring counter whose maximum buffer capacity is N. The buffer capacity N is fixed and the capacity cannot be dynamically adjusted.
Therefore, the FIFO buffer circuit has a problem that all of the area of the FIFO buffer is always operating to consume power, though all of the area is not always filled with data.
The control based on a remaining amount of “valid data”, which is remaining data in a buffer area that has been written but has not been read yet, is essentially ideal. However, such control cannot be performed on the conventional FIFO buffer circuit.